A redundantly repairable array device is one which contains a main array and spare elements, often built adjacent the main array, which can be substituted for defective original elements of the main array in order to repair it. A redundant memory device may, for example, be a rectangular array of memory cells each of whose elements, i.e., rows and columns, comprises a plurality of individual memory cells, and which also has several redundant rows and redundant columns of cells. If the main array contains a faulty cell, it can be repaired by replacing either the entire row or entire column which contain the faulty cell, with a redundant element. If several cells are faulty one or several redundant elements may be employed, and the choice of whether to repair a particular cell by replacing the row of which it is a member or the column of which it is a member, can be more difficult. Incorrect choice may result in exhaustion of the redundant elements before a complete repair plan has been devised and the consequent rejection of an array for which a correct choice would have enabled a complete repair. After assignments of redundant elements have been made to cover all of the faults, the memory array may be sent to a laser "trimmer" for execution of the repair plan. In some cases it may be impossible to devise a plan that would enable repair of all of the faults with the limited number of redundant elements that are available.
The use of redundant elements for repair can increase the yields of array products significantly. Bubble memory manufacturers have used the redundancy technique extensively, and it has become popular also in the manufacture of relatively high bit density devices such as 256K DRAMs.
Present techniques for assignment of redundant elements to faulty memory locations include a two step process. The first step would be to ascertain which elements of a memory array are faulty. The information obtained during this procedure along with information of the redundant rows and columns available would then be collated by means of an algorithm for computation of a replacement scheme which would result in an assignment of the redundant rows and columns in such a way to replace all of the defective memory locations, if such a replacement is then determined to be feasible.
The redundancy technique has some offsetting disadvantages, however, two of which are increased cost of testing the products and reduced throughput (average productivity). These disadvantages are related to the hardware and time that are required to determine whether the arrays are reparable and, if they are, what the repair instructions should be. Conventional array testers can require seconds or minutes to determine and specify the instructions that are required to make a repair. The time required to prepare repair instructions for an array has ordinarily been in addition to the time required to test it to identify its faulty cells. The result is small throughput, as few arrays can be tested and analyzed per hour. The invention is a cost-effective method and apparatus for alleviating these problems.